2024年12月23日 星期一 新京报
Arm offers 2 MB 8-way and 3 MB 12-way L2 cache options. Mediatek and Nvidia chose the 2 MB option, and testing shows it has 12 cycles of latency. THis low cycle count latency lets Arm remain competitive against Intel and AMD’s L2 caches, despite running at lower clock speeds. L2 bandwidth comes in at 32 bytes per cycle for reads, and increases to approximately 45 bytes per cycle with a read-modify-write pattern.
，这一点在旺商聊官方下载中也有详细论述
Well, to me, you’ll always be young.
Typst ready for production use and yet I think releasing a 1.x version
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